The collector base junction of T 1 is forward biased.

The emitter base junctions of T 1 are reverse biased. Output is high (that is Y=1).Ĭondition 2: Each input is high. T 4 functions as an emitter follower and couples a high voltage to load. T 2 is cut off and forces T 3 to cut off. Thus, the base voltage of T 2 is almost zero. The operation can be described briefly by three conditions as specified below:Ĭondition 1: At least one input is low (that is, 0). The voltage drop of diode D remains the base-emitter junction of T 4 reverse biased therefore only T 3 conducts while output is low. The diode D is added to make sure that T 4 is cut off while output is low. The transistors T 3 and T 4 by the totem pole output, the capacitance CL shows the stray capacitance and so on. The transistor T 2 functions as a phase splitter since the emitter voltage is out of phase along with the collector voltage. In this figure, T 1 has 3 emitters thus there can be three inputs A, B, C. Multiple emitter transistors along with about 60 emitters have been developed. Such transistor can be thought of like a combination of various transistors along with a common collector and base. T 1 is a multiple type emitter transistor. The low output impedance means a short time constant RC therefore the output can change rapidly from one state to the other. The totem pole output implies that transistor T 4 sits atop T 3 in order to give low output impedance. Operation of TTL NAND Gate: Fig.(d) Demonstrates a TTL NAND gate with a totem pole output. Give the circuit of a TTL NAND gate and explain its operation in brief.

Ttl nand gate with totem pole output